1. Field of the Invention
This invention relates to a random access semiconductor memory capable of both reading and writing. In particular, the invention relates to a large capacity dynamic semiconductor memory.
2. Description of the Related Art
With the advance in techniques for making smaller semiconductor memory elements, capacities have been progressively increased up to the present. However, recently the pace of shrinking memory element has slowed, and inevitably the rate at which capacities can be increased using binary data memory cells as used up to the present has slowed. This suggests the method whereby one cell is used to store a multivalued data. In this type of memory, a single memory cell does not store two valued binary data (one bit), but rather stores four values (two bit) or eight valued (three bit) data. In other words, in the case of n-valued memory, 1/n cells hold the same amount of data as in the conventional binary data system.
An example of this kind of multivalued data memory is described in "A16-levels/cell dynamic memory", pages 246-247 of Digest of Technical Papers ISSCC, 1985, or as disclosed in Japanese Patent Laying Open Specification Sho 50-62233 (1975), in which a set of digital signals are collected together, converted to an analogue signal, and that analogue signal is stored.
However, in the above described prior art, data is read out sequentially over a number of cycles, so that there is the drawback that access times are long. For example, of the above prior art, the former requires access times between 50 microseconds and 100 microseconds, and this value is between 100 and 1,000 times that for a normal binary dynamic RAM.
Further, in the former example it is necessary to control the potential of a word line in a stepwise fashion, and considerably difficult circuitry techniques are required for this level generation. Moreover, in the latter example, in order to produce write levels for a bit line, a large intermediate potential generation circuit is required for the drive current, and in this case also high level circuitry techniques are required.
Thus in this prior art, the principal objective of dynamic RAM design which is lower cost, is not met.
A semiconductor memory using this type of conventional multivalued data storage method has defects including long access time and high cost of manufacture.